1. Technical Field
The present disclosure relates to integrated circuit (IC) design, and more specifically to an optimal flow to design an IC operable in multiple timing modes.
2. Related Art
Circuits are often implemented to operate in multiple timing modes. Each timing mode is associated with a corresponding desired set of user level features such that the resource requirements (one or more of processing power, timing constraints, operation of different components, amount of memory space required, etc.) to provide the features corresponding to different modes are substantially different.
For example, an integrated circuit (IC) contained in a communication device such as a mobile phone, may be designed to provide video and audio features, and thus may be viewed as operable in a video mode, an audio mode, and a mode in which both video and audio are processed. Due to the different user level features provided in different timing modes, the resource requirements may be different in different timing modes.
In view of the differences of resource requirements, an IC may be designed to contain some circuit portions which operate (i.e., active to process signals) in the video mode (when providing video features, such as, for example, transferring or displaying images), other circuit portions that operate in the audio mode (to play music, for example), etc, and circuit portions that are operational in both video and audio modes. Alternatively or in addition, some portions may operate at different clock speeds while operating in different modes.
As is well known in the relevant arts, the design of a circuit (for example, an integrated circuit) generally follows a sequence of stages, commonly termed design flow, and which may be performed using corresponding electronic design automation (EDA) tools. A digital IC, for example, may first be specified/described in terms of the logic required to be implemented (e.g., via RTL coding using VHDL, Verilog, etc).
The logic description may generate an output specifying the various circuit components and their interconnections. The components and their interconnections may then be “placed and routed” to fit in a desired silicon die area. A timing analysis may then be performed on the placed-and-routed circuit to verify if timing of signals at various nodes is as desired. A final set of data completely describing the circuit may then be generated and provided for fabricating the IC.
Several challenges present themselves in the design flow while designing a circuit that may operate in multiple timing modes. It is generally desirable to render the design flow optimal (in terms reduced time, minimal computing and storage resources, etc) when designing such a circuit.